FIG. 1 illustrates a conventional integrator circuit, which includes an operational amplifier 105 configured with an integration capacitor (Cint) in the feedback loop to the inverting input. The non-inverting input of op-amp 105 is coupled to a bias, which could be, for example, a fixed DC voltage or ground. A reset switch is coupled across the integration capacitor. Such circuits are commonly used in numerous applications, such as in read-out circuits for imaging arrays, and particularly in infrared focal plane arrays (FPA).
In such applications, each cell of the FPA generates a detector current when a scene is imaged. Each detector current generated by the FPA is applied to the input of a corresponding integrator circuit included in the FPA read-out circuit. In operation, the integrator is reset by closing the reset switch, which initializes the integration process to a known starting voltage. The reset switch is then opened to begin integration. Any current (e.g., Iinput) then flowing into the input current node is integrated onto the integration capacitor.
When the reset switch is opened, some leakage or “offset” charge from the reset switch is injected into the inverting input of the op-amp 105 and effectively combines with the input current, Iinput. This charge manifests as an offset from the integrator's starting level, and is therefore referred to herein as an “offset charge” or “reset offset” or “reset offset charge” or “integrator offset” or simply “offset”. This offset can consume a large fraction of the voltage range of the integrator, especially if the integration capacitor is small.
Various conventional techniques are available that address integrator offset cancellation. However, such techniques generally require the addition of substantial circuitry and complexity, particularly for designs involving multiple integrator circuits, where each circuit must be modified with the substantial offset cancellation circuitry. Such additional circuitry adds cost and requires additional space, which may not be acceptable for space-limited applications. Moreover, the precise cancellation of the reset offset charge is not trivial. On one hand, the offset cancellation must be done so that only offset charge is cancelled, and not the desired input current. On the other hand, all of the offset charge must be removed, as any residual offset will still adversely impact the voltage range of the integrator.
What is needed, therefore, are techniques for removing offset charge associated with the reset switch.